1. Field of the Invention
The present invention relates to method and apparatus for reproducing information recorded on a recording medium, and more particularly, to a method and apparatus for reproducing information by using a phase-locked loop which generates a clock signal from a reproduced signal.
2. Related Background Art
Various information recording media, such as a disk, card and tape which record and reproduce information have been known in the art. Of those, a card-shaped optical information recording medium (hereinafter referred to as an optical card) is expected to have a big demand as a compact, light weight, easy-to-carry and large capacity information recording medium.
When digital record information is to be reproduced from such a medium, it is necessary to generate a clock signal (reproducing clock) to demodulate data from the reproduced signal. The clock signal is usually generated by a phase-locked loop (PLL) based on the reproduced signal.
FIG. 1 shows a block diagram of a conventional PLL circuit. Such a circuit includes a phase comparator 1, a lowpass filter 2 and a voltage controlled oscillator 3, connected in a series circuit. An output of the voltage controlled oscillator 3 is fed back to the phase comparator 1, which compares the reproduced signal from the recording medium (not shown) with the output of the voltage controlled oscillator 3 to produce a voltage output representing a phase difference therebetween. The low-pass filter (LPF) 2 passes only a low frequency component of the output of the phase comparator 1 and supplies it to the voltage controlled oscillator (VCO) 3. The VCO generates an output signal at a frequency corresponding to the output voltage of the LPF 2, as a reproducing clock.
The PLL circuit feeds the output signal of the VCO 3 back to the phase comparator 1 to control the VCO 3 such that the frequency and phase of the output signal of the VCO 3 are always equal to the frequency and phase of the reproduced signal, which is the input signal to the PLL circuit.
Assuming that transfer functions of the phase comparator 1, LPF 2 and VCO 3 are Kp, G and Kvco/S, respectively, a circulation transfer function Go of the PLL circuit is expressed by EQU Go=Kp.multidot.G.multidot.Kvco/S
It is important to determine a value of the transfer function Go.
If a gain or cutoff frequency of the function Go is high, the sensitivity of the PLL is high and the PLL may follow a variation in the frequency and phase of the detected signal. For example, when a transport velocity of the recording medium includes many jitters and the frequency and phase of the detected signal vary significantly, the PLL can follow the variation. On the other hand, if the sensitivity of the PLL is high, auto-tracking may be disabled by a defect, such as a scratch or dust on the recording medium so that asynchronization may readily take place when the reproduced signal drops.
On the other hand, if the gain or cutoff frequency of the transfer function Go is low to lower the sensitivity of the PLL, the PLL cannot follow the jitter and asynchronization may readily take place, but the PLL is less sensitive to the defect, such as a scratch and dust, on the recording medium.
In the conventional information reproducing apparatus, the gain or cutoff frequency of the transfer function Go which determines the sensitivity of the PLL circuit is fixed to a value inherent to the apparatus. Accordingly, it is difficult to set the sensitivity of the PLL circuit to solve both problems of jitter and the drop of the reproduced signal. In the information reproducing apparatus which uses an optical card, the optical card is reciprocally moved. As a result, an impact at the reversal adversely affects the tracking control. Thereby, the drop of the reproduced signal and asynchronization readily take place.
An apparatus for reproducing information which holds the tracking signal when the reproduced signal drops is disclosed in Japanese Laid-Open Patent Application No. 59-142757. When the above sample/hold technique is applied to the PLL circuit, a configuration shown in FIG. 2 is formed. In FIG. 2, like elements to those shown in FIG. 1 are designated by like numerals and detailed explanation thereof is omitted.
The circuit of FIG. 2 differs from the circuit of FIG. 1 in that a reproduced signal drop detector 4, which detects the drop of the reproduced signal to generate a data drop signal S.sub.1, and a sample/hold (S/H) circuit 5 connected between the LPF 2 and the VCO 3 for supplying the output of the LPF 2 to the VCO 3 in a normal state, but sampling and holding the output of the LPF 2 when the data drop signal S.sub.1 is generated, are added.
When the reproduced signal drops, a residual phase error of the PLL generally increases with time in accordance with the circulation transfer function Go of the PLL. When the residual phase error reaches 180 degrees (.pi.), asynchronization of the PLL takes place. The lower the gain of the transfer function Go is and the lower the cutoff frequency is, the longer is the time period in which the residual phase error reaches 180 degrees. Accordingly, it is desirable to lower the gain of the transfer function Go and the cutoff frequency in order to avoid adverse influence of a defect such as a scratch and dust, but when they are lowered, the PLL cannot follow the jitter and the asynchronization may take place.
In FIG. 2, the gain of the transfer function Go and the cutoff frequency are set sufficiently high, Thereby, the PLL can follow the jitter, and when the reproduced signal drops, the output of the LPF 2 is sampled and held by the S/H circuit 5, having a sufficiently long hold time constant, to fix the input voltage to the VCO 3 to a level which almost causes the drop of the reproduced signal accordingly, that the output frequency and phase of the VCO 3 are fixed to avoid asynchronization of the PLL circuit
In FIG. 2, if the dropped reproduced signal is recovered, the data drop signal S.sub.1 transits immediately after recovery of the signal (depending on the response characteristic of the reproduced signal drop detector 4). Acccordingly, holding by the S/H circuit 5 is released at that moment and the PLL circuit controls the phase error at that moment be rendered zero.
Critical factors in this case are the sensitivity of the PLL circuit and the sampled and held value, that is, a difference between the phase error at the time of drop of the signal and the phase error at the time of recovery of the signal.
Since the phase error at the time of drop of the signal and the phase error at the time of recovery of the signal are totally independent from each other, if the difference is large, the input to the VCO 3 changes stepwise. When the sensitivity of the PLL is high, the response characteristic includes, more or less, an overshoot. Accordingly, if there is a big change in the phase error, so that the input to the VCO 3 changes stepwise, the PLL may be asynchronized at the time of recovery of the signal due to the response characteristic.